Graduate Project
Field
AI, Hardware Security
Institution
RIT
Year
2024
Project Type
Individual
Advisor
Dr. Michael Zuzak
Keywords
Optical side-channel attacks, Integrated Circuits, Intellectual Property, Graph Neural Networks, Hardware security, Key information leakage​
Project Disclaimer:
Please note that the details provided about the ongoing project on this webpage are intentionally vague and generalized. This project is currently under research and development, and aspects of it may be subject to publication in the near future. In order to preserve the integrity of the research process and uphold the standards of academic publication, specific methodologies, results, and innovations cannot be disclosed at this time. The information presented is designed to offer a broad overview of the project's objectives, scope, and potential impact without compromising the novelty and proprietary elements of the research. We appreciate your understanding and interest in this project and look forward to sharing more detailed findings and developments upon completion of the research and through the proper academic channels.
Thank you for your understanding!
Project Highlights
This project explores an innovative method for enhancing the security of Integrated Circuits (ICs) against optical side-channel attacks, a crucial concern in the era of outsourced IC fabrication. By harnessing the power of Graph Neural Networks (GNNs), the initiative seeks to safeguard high-value Intellectual Property (IP) within these circuits, which are vulnerable during production in untrusted facilities. The project stands at the intersection of hardware security and advanced computational techniques, offering a fresh perspective on protecting ICs from emerging threats.
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Objective: To develop a novel method using GNNs for assessing and mitigating optical side-channel leakage risks in IC designs.
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Background: Addresses the challenge of securing high-value IP embedded in ICs produced in untrusted fabrication facilities.
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Innovation: Introduces the use of GNNs to identify potential key information leakage areas within a chip, enabling preemptive security enhancements.
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Methodology: Involves creating a cost function to quantify optical key leakage and training a GNN to estimate this cost across the circuit.
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Impact: Aims to significantly reduce the runtime for leakage estimation, offering a more efficient alternative to traditional, computationally intensive methods.
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Application: The approach has broad implications for a wide range of IC applications, from corporate to military, where the integrity of IP is paramount.
1: Sample EOFM probing process. A) EOFM probing setup. B) Sample data from EOFM probing.
Credit: M. Zuzak, Y. Liu, I. McDaniel and A. Srivastava, "A Combined Logical and Physical Attack on Logic Obfuscation," 2022 IEEE/ACM International Conference On Computer Aided Design (ICCAD), San Diego, CA, USA, 2022, pp. 1-9.